1. Introduction. - 1. 1. The Application Domain. - 1. 2. Knowledge Sources. - 1. 3. Book Organization. - References. - 2. Application Domain: Routing Algorithms. - 2. 1. Routing Algorithms. - 2. 2. Application Domain: Maze Routers. - 2. 3. Maze Router Varieties. - 2. 4. Why Choose Maze Routers?. - 2. 5. Chapter Summary. - References. - 3. Software Reusability. - 3. 1. Composition-Based Systems. - 3. 2. Generation-Based Systems. - 3. 3. Chapter Summary. - References. - 4. ELF: A Program Synthesis Architecture. - 4. 1. Combining Router Knowledge with Program Synthesis Knowledge. - 4. 2. Algorithm Schema Representation. - 4. 3. Data Structure Style Representation. - 4. 4. Intermediate Representation for Synthesized Code. - 4. 5. Domain Knowledge Representation Using a Rule-Based System. - 4. 6. Architecture Overview. - 4. 7. Architecture Overview. - 4. 8. Chapter Summary. - References. - 5. The Input Stage. - 5. 1. Input Stage Operation. - 5. 2. Input Stage Rule Types. - 5. 3. Chapter Summary. - References. - 6. The Selection Stage. - 6. 1. Selection Control Module. - 6. 2. The Dependency Analysis Module. - 6. 3. The Data Structure Designer Module. - 6. 4. The Algorithm Designer Module. - 6. 5. Chapter Summary. - References. - 7. The Code Generator Stage. - 7. 1. I/O Operation Synthesis. - 7. 2. The Use of Router Domain Knowledge in the Transformation Process. - 7. 3. Stepwise Refinement in the Transformation Process. - 7. 4. Chapter Summary. - References. - 8. Implementation. - 8. 1. Implementation Characteristics. - 8. 2. Design History. - 8. 3. Modifying ELF: Is It Really Better?. - 8. 4. Issues in Debugging ELF-synthesized Code. - 8. 5. Chapter Summary. - References. - 9. ELF Validation. - 9. 1. Experimental Methodology. - 9. 2. Gate Array Style Routers. - 9. 3. Printed Circuit Board Style Router. - 9. 4. Macro-Cell IC Style Router. - 9. 5. Chapter Summary. - References. - 10. Conclusion. - 10. 1. Summary. - 10. 2. ELF: Hindsight and Evolution. - References. - Appendix I. Router Specification Manual. - I. 1. Syntax Description. - I. 2. Constraint Level Structure. - I. 2. 1. Top-Level Constraint Specifications. - I. 2. 2. Aigorithm Constraints. - I. 2. 2. 1. Net_sorting. - I. 2. 2. 2. Node_sorting. - I. 2. 2. 3. Cost_function. - I. 2. 2. 4. Netlist. - I. 2. 2. 5. Output. - I. 2. 2. 6. Expansion. - I. 2. 2. 7. Net_composition. - I. 2. 2. 8. Routing_composition. - I. 2. 3. Application Constraints. - I. 2. 3. 1. Type. - I. 2. 3. 2. Sub type. - I. 2. 3. 3. Alg_type. - I. 2. 3. 4. Number_of_nets. - I. 2. 3. 5. Number_of_cells_per_net. - I. 2. 4. Fabrication Constraints. - I. 2. 4. 1. Units. - I. 2. 4. 2. Pads. - I. 2. 4. 3. Connections. - I. 2. 4. 4. Xsize YsizeZsize. - I. 2. 4. 5. Technology. - I. 2. 4. 6. PCB. - I. 2. 4. 7. Number_of_layers. - I. 2. 4. 8. Available_via_positioning. - I. 2. 4. 9. Layer. - I. 2. 4. 10. IC. - I. 3. Input constraint Schemes. Language: English